IEC 62530:2021 Systemverilog - 统一的硬件设计 规范和验证语言

标准编号：IEC 62530:2021

中文名称：Systemverilog - 统一的硬件设计 规范和验证语言

英文名称：SystemVerilog - Unified Hardware Design, Specification, and Verification Language

发布日期：2021-07-26

标准范围

IEC 62530:2021（E）为IEEE 1800提供了语言语法和语义的定义？SystemVerilog语言，这是一种统一的硬件设计、规范和验证语言。该标准包括对行为、寄存器传输级（RTL）和门级硬件描述的支持；测试台、覆盖、断言、面向对象和约束随机构造；并且还向外国编程语言提供应用程序编程接口（API）。此版本更正了IEEE Std 1800-2012.1中语言定义的错误并澄清了各个方面。此版本还提供了增强的功能，可简化设计、改进验证并增强跨语言交互。该出版物具有双标志IEEE/IEC标准的地位。

IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800？ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.
This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
This publication has the status of a double logo IEEE/IEC standard.

标准预览图